View ATTINY2313A-14_8396043.PDF datasheet online --- IC-ON-LINE

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features ? high performance, low power avr ? 8-bit microcontroller ? advanced risc architecture ? 120 powerful instructions ? most single clock cycle execution ? 32 x 8 general purpose working registers ? fully static operation ? up to 20 mips throughput at 20 mhz ? data and non-volatile program and data memories ? 2/4k bytes of in-system self programmable flash ? endurance 10,000 write/erase cycles ? 128/256 bytes in-system programmable eeprom ? endurance: 100,000 write/erase cycles ? 128/256 bytes internal sram ? programming lock fo r flash program and eeprom data security ? peripheral features ? one 8-bit timer/counter with se parate prescaler and compare mode ? one 16-bit timer/counter with separate prescaler, compare and capture modes ?four pwm channels ? on-chip analog comparator ? programmable watchdog timer with on-chip oscillator ? usi ? universal serial interface ? full duplex usart ? special microcontroller features ? debugwire on-chip debugging ? in-system programmable via spi port ? external and internal interrupt sources ? low-power idle, power-down, and standby modes ? enhanced power-on reset circuit ? programmable brown-out detection circuit ? internal calibrated oscillator ? i/o and packages ? 18 programmable i/o lines ? 20-pin pdip, 20-pin soic, 20-pad mlf/vqfn ? operating voltage ? 1.8 ? 5.5v ? speed grades ? 0 ? 4 mhz @ 1.8 ? 5.5v ? 0 ? 10 mhz @ 2.7 ? 5.5v ? 0 ? 20 mhz @ 4.5 ? 5.5v ? industrial temperature range: -40 c to +85 c ? low power consumption ? active mode ? 190 a at 1.8v and 1mhz ?idle mode ? 24 a at 1.8v and 1mhz ? power-down mode ? 0.1 a at 1.8v and +25 c 8-bit microcontroller with 2/4k bytes in-system programmable flash attiny2313a attiny4313 summary rev. 8246bs?avr?09/11
2 8246bs?avr?09/11 attiny2313a/4313 1. pin configurations figure 1-1. pinout attiny2313a/4313 (pcint10/reset/dw) pa2 (pcint11/rxd) pd0 (pcint12/txd) pd1 (pcint9/xtal2) pa1 (pcint8/clki/xtal1) pa0 (pcint13/ckout/xck/int0) pd2 (pcint14/int1) pd3 (pcint15/t0) pd4 (pcint16/oc0b/t1) pd5 gnd 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 vcc pb7 (usck/scl/sck/pcint7) pb6 (miso/do/pcint6) pb5 (mosi/di/sda/pcint5) pb4 (oc1b/pcint4) pb3 (oc1a/pcint3) pb2 (oc0a/pcint2) pb1 (ain1/pcint1) pb0 (ain0/pcint0) pd6 (icpi/pcint17) pdip/soic 1 2 3 4 5 mlf/vqfn 15 14 13 12 11 20 19 18 17 16 6 7 8 9 10 (pcint12/txd) pd1 (pcint9/xtal2) pa1 (pcint8/clki/xtal1) pa0 (pcint13/ckout/xck/int0) pd2 (pcint14/int1) pd3 (pcint15/t0) pd4 (pcint16/oc0b/t1) pd5 gnd (pcint17/icpi) pd6 (ain0/pcint0) pb0 pb5 (mosi/di/sda/pcint5) pb4 (oc1b/pcint4) pb3 (oc1a/pcint3) pb2 (oc0a/pcint2) pb1 (ain1/pcint1) pd0 (rxd/pcint11) pa2 (reset/dw/pcint10) vcc pb7 (usck/scl/sck/pcint7) pb6 (miso/do/pcint6) note: bottom pad should be soldered to ground.
3 8246bs?avr?09/11 attiny2313a/4313 1.1 pin descriptions 1.1.1 vcc digital supply voltage. 1.1.2 gnd ground. 1.1.3 port a (pa2..pa0) port a is a 3-bit bi-directional i/o port with inte rnal pull-up resistors (selected for each bit). the port a output buffers have symmetrical drive characteristics with both high sink and source capability, except pa2 which has the reset capability. to use pin pa2 as i/o pin, instead of reset pin, program (?0?) rstdisbl fuse. as input s, port a pins that are externally pulled low will source current if the pull-up resistors are activated. the port a pins are tri-stated when a reset condition becomes active, even if the clock is not running. port a also serves the functions of various special features of the attiny2313a/4313 as listed on page 61 . 1.1.4 port b (pb7..pb0) port b is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port b output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port b pi ns that are externally pulled low will source current if the pull-up resistors are activated. the port b pins are tri-stated when a reset condition becomes active, even if the clock is not running. port b also serves the functions of various special features of the attiny2313a/4313 as listed on page 62 . 1.1.5 port d (pd6..pd0) port d is a 7-bit bi-directional i/o port with inte rnal pull-up resistors (selected for each bit). the port d output buffers have symmetrical drive c haracteristics with bot h high sink and source capability. as inputs, port d pi ns that are externally pulled lo w will source current if the pull-up resistors are activated. the port d pins are tri-stated when a reset condition becomes active, even if the clock is not running. port d also serves the functions of various special features of the attiny2313a/4313 as listed on page 66 . 1.1.6 reset reset input. a low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running and provided that the reset pin has not been disabled. the minimum pulse length is given in table 22-3 on page 201 . shorter pulses are not guaranteed to generate a reset. the reset input is an alternate function for pa2 and dw. the reset pin can also be used as a (weak) i/o pin. 1.1.7 xtal1 input to the inverting oscillator amplifier and input to the internal clock operating circuit. xtal1 is an alternate function for pa0.
4 8246bs?avr?09/11 attiny2313a/4313 1.1.8 xtal2 output from the inverting osc illator amplifier. xtal2 is an alternate function for pa1.
5 8246bs?avr?09/11 attiny2313a/4313 2. overview the attiny2313a/4313 is a low-power cmos 8- bit microcontroller based on the avr enhanced risc architecture. by executing powerful instructions in a single clock cycle, the attiny2313a/4313 achieves throughputs approach ing 1 mips per mhz allowing the system designer to optimize power consum ption versus processing speed. 2.1 block diagram figure 2-1. block diagram program counter program flash instruction register gnd vcc instruction decoder control lines stack pointer sram general purpose register alu status register programming logic spi 8-bit data bus xtal1 xtal2 reset internal oscillator oscillator watchdog timer timing and control mcu control register mcu status register timer/ counters interrupt unit eeprom usi usart analog comparator data register portb data dir. reg. portb data register porta data dir. reg. porta portb drivers pb0 - pb7 porta drivers pa0 - pa2 data register portd data dir. reg. portd portd drivers pd0 - pd6 on-chip debugger internal calibrated oscillator
6 8246bs?avr?09/11 attiny2313a/4313 the avr core combines a rich instruction set with 32 general purpose working registers. all the 32 registers are directly connected to the arithmetic logic unit (alu), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. the resulting architecture is more code efficient while achiev ing throughputs up to ten times faster than con- ventional cisc microcontrollers. the attiny2313a/4313 provides the following features: 2/4k bytes of in-system programmable flash, 128/256 bytes eeprom, 12 8/256 bytes sram, 18 general pu rpose i/o lines, 32 general purpose working registers, a single-wire interface for on-chip debugging, two flexible timer/counters with compare modes, internal and external interrupts, a serial programmable usart, universal serial interface with start condition detector, a programmable watchdog timer with internal oscillator, an d three software selectable powe r saving modes. the idle mode stops the cpu while allowing the sram, timer/counters, and interrupt system to continue func- tioning. the power-down mode saves the register contents but freezes th e oscillator, disabling all other chip functions until the next interrupt or hardware reset. in standby mode, the crys- tal/resonator oscillator is running while the rest of the device is sleeping. this allows very fast start-up combined with low-power consumption. the device is manufactured using atmel?s high density non-volatile memory technology. the on-chip isp flash allows the program memory to be reprogrammed in-system through an spi serial interface, or by a conventional non-vol atile memory programmer. by combining an 8-bit risc cpu with in-system self-programmable flash on a monolithic chip, the atmel attiny2313a/4313 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. the attiny2313a/4313 avr is supported with a full suite of program and system development tools including: c compilers, macro assemblers, program debugger/simulators, in-circuit emu- lators, and evaluation kits. 2.2 comparison between at tiny2313a and attiny4313 the attiny2313a and attiny4313 differ only in memory sizes. table 2-1 summarizes the differ- ent memory sizes for the two devices. table 2-1. memory size summary device flash eeprom ram attiny2313a 2k bytes 128 bytes 128 bytes attiny4313 4k bytes 256 bytes 256 bytes
7 8246bs?avr?09/11 attiny2313a/4313 3. about 3.1 resources a comprehensive set of drivers, application notes, data sheets and descriptions on development tools are available for download at http://www.atmel.com/avr. 3.2 code examples this documentation contains simple code examples that briefly show how to use various parts of the device. these code examples assume that the part specific header file is included before compilation. be aware that not all c compiler vendors include bit definitions in the header files and interrupt handling in c is compiler dependent. please confirm with the c compiler documen- tation for more details. for i/o registers located in the extended i/o map, ?in?, ?out?, ?sbis?, ?sbic?, ?cbi?, and ?sbi? instructions must be replaced with instructions that allow access to extended i/o. typically, this means ?lds? and ?sts? combined with ?sbrs?, ?s brc?, ?sbr?, and ?cbr?. note that not all avr devices include an extended i/o map. 3.3 data retention reliability qualification results show that the pr ojected data retention failure rate is much less than 1 ppm over 20 years at 85c or 100 years at 25c.
8 8246bs?avr?09/11 attiny2313a/4313 4. register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page 0x3f (0x5f) sreg i t h s v n z c 9 0x3e (0x5e) reserved ? ? ? ? ? ? ? ? 0x3d (0x5d) spl sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 12 0x3c (0x5c) ocr0b timer/counter0 ? compare register b 85 0x3b (0x5b) gimsk int1 int0 pcie0 pcie2 pcie1 ? ? ?50 0x3a (0x5a) gifr intf1 intf0 pcif0 pcif2 pcif1 ? ? ?51 0x39 (0x59) timsk toie1 ocie1a ocie1b ? icie1 ocie0b toie0 ocie0a 86, 115 0x38 (0x58) tifr tov1 ocf1a ocf1b ? icf1 ocf0b tov0 ocf0a 86, 115 0x37 (0x57) spmcsr ? ? rsig ctpb rflb pgwrt pgers spmen 175 0x36 (0x56) ocr0a timer/counter0 ? compare register a 85 0x35 (0x55) mcucr pud sm1 se sm0 isc11 isc10 isc01 isc00 36, 50, 68 0x34 (0x54) mcusr ? ? ? ? wdrf borf extrf porf 44 0x33 (0x53) tccr0b foc0a foc0b ? ? wgm02 cs02 cs01 cs00 84 0x32 (0x52) tcnt0 timer/counter0 (8-bit) 85 0x31 (0x51) osccal ? cal6 cal5 cal4 cal3 cal2 cal1 cal0 31 0x30 (0x50) tccr0a com0a1 com0a0 com0b1 com0b0 ? ?wgm01wgm00 81 0x2f (0x4f) tccr1a com1a1 com1a0 com1b1 com1b0 ? ? wgm11 wgm10 110 0x2e (0x4e) tccr1b icnc1 ices1 ? wgm13 wgm12 cs12 cs11 cs10 112 0x2d (0x4d) tcnt1h timer/counter1 ? counter register high byte 114 0x2c (0x4c) tcnt1l timer/counter1 ? counter register low byte 114 0x2b (0x4b) ocr1ah timer/counter1 ? compare register a high byte 114 0x2a (0x4a) ocr1al timer/counter1 ? compare register a low byte 114 0x29 (0x49) ocr1bh timer/counter1 ? compare register b high byte 114 0x28 (0x48) ocr1bl timer/counter1 ? compare register b low byte 114 0x27 (0x47) reserved ? ? ? ? ? ? ? ? 0x26 (0x46) clkpr clkpce ? ? ? clkps3 clkps2 clkps1 clkps0 31 0x25 (0x45) icr1h timer/counter1 - input capture register high byte 114 0x24 (0x44) icr1l timer/counter1 - input capture register low byte 114 0x23 (0x43) gtccr ? ? ? ? ? ? ? psr10 118 0x22 (ox42) tccr1c foc1a foc1b ? ? ? ? ? ? 113 0x21 (0x41) wdtcsr wdif wdie wdp3 wdce wde wdp2 wdp1 wdp0 44 0x20 (0x40) pcmsk0 pcint7 pcint6 pcint5 pcint4 pcint3 pcint2 pcint1 pcint0 53 0x1f (0x3f) reserved ? ? ? ? ? ? ? ? 0x1e (0x3e) eear ? eeprom address register 23 0x1d (0x3d) eedr eeprom data register 23 0x1c (0x3c) eecr ? ? eepm1 eepm0 eerie eempe eepe eere 23 0x1b (0x3b) porta ? ? ? ? ? porta2 porta1 porta0 68 0x1a (0x3a) ddra ? ? ? ? ? dda2 dda1 dda0 68 0x19 (0x39) pina ? ? ? ? ? pina2 pina1 pina0 69 0x18 (0x38) portb portb7 portb6 portb 5 portb4 portb3 portb2 portb1 portb0 69 0x17 (0x37) ddrb ddb7 ddb6 ddb 5 ddb4 ddb3 ddb2 ddb1 ddb0 69 0x16 (0x36) pinb pinb7 pinb6 pinb5 pinb4 pinb3 pinb2 pinb1 pinb0 69 0x15 (0x35) gpior2 general purpose i/o register 2 24 0x14 (0x34) gpior1 general purpose i/o register 1 24 0x13 (0x33) gpior0 general purpose i/o register 0 24 0x12 (0x32) portd ? portd6 portd5 portd4 portd3 portd2 portd1 portd0 69 0x11 (0x31) ddrd ? ddd6 ddd5 ddd4 ddd3 ddd2 ddd1 ddd0 69 0x10 (0x30) pind ? pind6 pind5 pind4 pind3 pind2 pind1 pind0 69 0x0f (0x2f) usidr usi data register 165 0x0e (0x2e) usisr usisif usioif usipf usidc usicnt3 usicnt2 usicnt1 usicnt0 164 0x0d (0x2d) usicr usisie usioie usiwm1 usiwm0 usics1 usics0 usiclk usitc 162 0x0c (0x2c) udr uart data register (8-bit) 136 0x0b (0x2b) ucsra rxc txc udre fe dor upe u2x mpcm 137 0x0a (0x2a) ucsrb rxcie txcie udrie rxen txen ucsz2 rxb8 txb8 138 0x09 (0x29) ubrrl ubrrh[7:0] 140 0x08 (0x28) acsr acd acbg aco aci acie acic acis1 acis0 167 0x07 (0x27) bodcr ? ? ? ? ? ?bodsbodse 37 0x06 (0x26) prr ? ? ? ? prtim1 prtim0 prusi prusart 36 0x05 (0x25) pcmsk2 ? pcint17 pcint16 pcint15 pcint14 pcint13 pcint12 pcint11 52 0x04 (0x24) pcmsk1 ? ? ? ? ? pcint10 pcint9 pcint8 52 0x03 (0x23) ucsrc umsel1 umsel 0 upm1 upm0 usbs ucsz1 ucsz0 ucpol 139 0x02 (0x22) ubrrh ? ? ? ? ubrrh[11:8] 140 0x01 (0x21) didr ? ? ? ? ? ? ain1d ain0d 168 0x00 (0x20) usibr usi buffer register 166
9 8246bs?avr?09/11 attiny2313a/4313 notes: 1. for compatibility with future devices, reserved bits s hould be written to zero if accessed. reserved i/o memory address es should never be written. 2. i/o registers within the address range 0x00 - 0x1f are directly bit-accessible using the sbi and cbi instructions. in these registers, the value of single bits can be ch ecked by using the sbis and sbic instructions. 3. some of the status flags are cleared by writing a logical o ne to them. note that, unlike most other avrs, the cbi and sbi instructions will only operate on the specif ied bit, and can therefore be used on regi sters containing such status flags. the cbi and sbi instructions work wit h registers 0x00 to 0x1f only. 4. when using the i/o specific commands in and out, the i/o addresses 0x00 - 0x3f must be used. when addressing i/o registers as data space using ld and st instru ctions, 0x20 must be added to these addresses.
10 8246bs?avr?09/11 attiny2313a/4313 5. instruction set summary mnemonics operands description operation flags #clocks arithmetic and logic instructions add rd, rr add two registers rd rd + rr z,c,n,v,h 1 adc rd, rr add with carry two registers rd rd + rr + c z,c,n,v,h 1 adiw rdl,k add immediate to word rdh:rdl rdh:rdl + k z,c,n,v,s 2 sub rd, rr subtract two registers rd rd - rr z,c,n,v,h 1 subi rd, k subtract constant from register rd rd - k z,c,n,v,h 1 sbc rd, rr subtract with carry two registers rd rd - rr - c z,c,n,v,h 1 sbci rd, k subtract with carry constant from reg. rd rd - k - c z,c,n,v,h 1 sbiw rdl,k subtract immediate from word rdh:rdl rdh:rdl - k z,c,n,v,s 2 and rd, rr logical and registers rd rd ? rr z,n,v 1 andi rd, k logical and register and constant rd rd ? k z,n,v 1 or rd, rr logical or registers rd rd v rr z,n,v 1 ori rd, k logical or register and constant rd rd v k z,n,v 1 eor rd, rr exclusive or registers rd rd rr z,n,v 1 com rd one?s complement rd 0xff ? rd z,c,n,v 1 neg rd two?s complement rd 0x00 ? rd z,c,n,v,h 1 sbr rd,k set bit(s) in register rd rd v k z,n,v 1 cbr rd,k clear bit(s) in register rd rd ? (0xff - k) z,n,v 1 inc rd increment rd rd + 1 z,n,v 1 dec rd decrement rd rd ? 1 z,n,v 1 tst rd test for zero or minus rd rd ? rd z,n,v 1 clr rd clear register rd rd rd z,n,v 1 ser rd set register rd 0xff none 1 branch instructions rjmp k relative jump pc pc + k + 1 none 2 ijmp indirect jump to (z) pc z none 2 rcall k relative subroutine call pc pc + k + 1 none 3 icall indirect call to (z) pc znone3 ret subroutine return pc stack none 4 reti interrupt return pc stack i 4 cpse rd,rr compare, skip if equal if (rd = rr) pc pc + 2 or 3 none 1/2/3 cp rd,rr compare rd ? rr z, n,v,c,h 1 cpc rd,rr compare with carry rd ? rr ? c z, n,v,c,h 1 cpi rd,k compare register with immediate rd ? k z, n,v,c,h 1 sbrc rr, b skip if bit in register cleared if (rr(b)=0) pc pc + 2 or 3 none 1/2/3 sbrs rr, b skip if bit in register is set if (rr(b)=1) pc pc + 2 or 3 none 1/2/3 sbic p, b skip if bit in i/o register cleared if (p(b)=0) pc pc + 2 or 3 none 1/2/3 sbis p, b skip if bit in i/o register is set if (p(b)=1) pc pc + 2 or 3 none 1/2/3 brbs s, k branch if status flag set if (sreg(s) = 1) then pc pc+k + 1 none 1/2 brbc s, k branch if status flag cleared if (sreg(s) = 0) then pc pc+k + 1 none 1/2 breq k branch if equal if (z = 1) then pc pc + k + 1 none 1/2 brne k branch if not equal if (z = 0) then pc pc + k + 1 none 1/2 brcs k branch if carry set if (c = 1) then pc pc + k + 1 none 1/2 brcc k branch if carry cleared if (c = 0) then pc pc + k + 1 none 1/2 brsh k branch if same or higher if (c = 0) then pc pc + k + 1 none 1/2 brlo k branch if lower if (c = 1) then pc pc + k + 1 none 1/2 brmi k branch if minus if (n = 1) then pc pc + k + 1 none 1/2 brpl k branch if plus if (n = 0) then pc pc + k + 1 none 1/2 brge k branch if greater or equal, signed if (n v= 0) then pc pc + k + 1 none 1/2 brlt k branch if less than zero, signed if (n v= 1) then pc pc + k + 1 none 1/2 brhs k branch if half carry flag set if (h = 1) then pc pc + k + 1 none 1/2 brhc k branch if half carry flag cleared if (h = 0) then pc pc + k + 1 none 1/2 brts k branch if t flag set if (t = 1) then pc pc + k + 1 none 1/2 brtc k branch if t flag cleared if (t = 0) then pc pc + k + 1 none 1/2 brvs k branch if overflow flag is set if (v = 1) then pc pc + k + 1 none 1/2 brvc k branch if overflow flag is cleared if (v = 0) then pc pc + k + 1 none 1/2 brie k branch if interrupt enabled if ( i = 1) then pc pc + k + 1 none 1/2 brid k branch if interrupt disabled if ( i = 0) then pc pc + k + 1 none 1/2 bit and bit-test instructions sbi p,b set bit in i/o register i/o(p,b) 1none2 cbi p,b clear bit in i/o register i/o(p,b) 0none2 lsl rd logical shift left rd(n+1) rd(n), rd(0) 0 z,c,n,v 1 lsr rd logical shift right rd(n) rd(n+1), rd(7) 0 z,c,n,v 1 rol rd rotate left through carry rd(0) c,rd(n+1) rd(n),c rd(7) z,c,n,v 1
11 8246bs?avr?09/11 attiny2313a/4313 ror rd rotate right through carry rd(7) c,rd(n) rd(n+1),c rd(0) z,c,n,v 1 asr rd arithmetic shift right rd(n) rd(n+1), n=0..6 z,c,n,v 1 swap rd swap nibbles rd(3..0) rd(7..4),rd(7..4) rd(3..0) none 1 bset s flag set sreg(s) 1 sreg(s) 1 bclr s flag clear sreg(s) 0 sreg(s) 1 bst rr, b bit store from register to t t rr(b) t 1 bld rd, b bit load from t to register rd(b) tnone1 sec set carry c 1c1 clc clear carry c 0 c 1 sen set negative flag n 1n1 cln clear negative flag n 0 n 1 sez set zero flag z 1z1 clz clear ze ro flag z 0 z 1 sei global interrupt enable i 1i1 cli global interrupt disable i 0 i 1 ses set signed test flag s 1s1 cls clear signed test flag s 0 s 1 sev set twos complement overflow. v 1v1 clv clear twos complement overflow v 0 v 1 set set t in sreg t 1t1 clt clear t in sreg t 0 t 1 seh set half carry flag in sreg h 1h1 clh clear half carry flag in sreg h 0 h 1 data transfer instructions mov rd, rr move between registers rd rr none 1 movw rd, rr copy register word rd+1:rd rr+1:rr none 1 ldi rd, k load immediate rd knone1 ld rd, x load indirect rd (x) none 2 ld rd, x+ load indirect and post-inc. rd (x), x x + 1 none 2 ld rd, - x load indirect and pre-dec. x x - 1, rd (x) none 2 ld rd, y load indirect rd (y) none 2 ld rd, y+ load indirect and post-inc. rd (y), y y + 1 none 2 ld rd, - y load indirect and pre-dec. y y - 1, rd (y) none 2 ldd rd,y+q load indirect with displacement rd (y + q) none 2 ld rd, z load indirect rd (z) none 2 ld rd, z+ load indirect and post-inc. rd (z), z z+1 none 2 ld rd, -z load indirect and pre-dec. z z - 1, rd (z) none 2 ldd rd, z+q load indirect with displacement rd (z + q) none 2 lds rd, k load direct from sram rd (k) none 2 st x, rr store indirect (x) rr none 2 st x+, rr store indirect and post-inc. (x) rr, x x + 1 none 2 st - x, rr store indirect and pre-dec. x x - 1, (x) rr none 2 st y, rr store indirect (y) rr none 2 st y+, rr store indirect and post-inc. (y) rr, y y + 1 none 2 st - y, rr store indirect and pre-dec. y y - 1, (y) rr none 2 std y+q,rr store indirect with displacement (y + q) rr none 2 st z, rr store indirect (z) rr none 2 st z+, rr store indirect and post-inc. (z) rr, z z + 1 none 2 st -z, rr store indirect and pre-dec. z z - 1, (z) rr none 2 std z+q,rr store indirect with displacement (z + q) rr none 2 sts k, rr store direct to sram (k) rr none 2 lpm load program memory r0 (z) none 3 lpm rd, z load program memory rd (z) none 3 lpm rd, z+ load program memory and post-inc rd (z), z z+1 none 3 spm store program memory (z) r1:r0 none - in rd, p in port rd pnone1 out p, rr out port p rr none 1 push rr push register on stack stack rr none 2 pop rd pop register from stack rd stack none 2 mcu control instructions nop no operation none 1 sleep sleep (see specific descr. for sleep function) none 1 wdr watchdog reset (see specific descr. for wdr/timer) none 1 break break for on-chip debug only none n/a mnemonics operands description operation flags #clocks
12 8246bs?avr?09/11 attiny2313a/4313 6. ordering information notes: 1. for speed vs. supply voltage, see section 22.3 ?speed? on page 199 . 2. all packages are pb-free, halide-free and fully green, and th ey comply with the european directive for restriction of hazard- ous substances (rohs). 3. code indicators: ? h: nipdau lead finish ? u or n: matte tin ? r: tape & reel 4. can also be supplied in wafer form. contact your local atme l sales office for ordering information and minimum quantities. 5. nipdau finish 6. topside markings : ? 1st line: t2313 ? 2nd line: axx ? 3rd line: xxx 6.1 attiny2313a speed (mhz) (1) supply voltage (v) temperature range package (2) ordering code (3) 20 1.8 ? 5.5 industrial (-40 c to +85 c) (4) 20p3 attiny2313a-pu 20s attiny2313a-su attiny2313a-sur 20m1 attiny2313a-mu attiny2313a-mur 20m2 (5)(6) attiny2313a-mmh attiny2313a-mmhr package type 20p3 20-lead, 0.300" wide, plastic dual inline package (pdip) 20s 20-lead, 0.300" wide, plastic gull wing small outline package (soic) 20m1 20-pad, 4 x 4 x 0.8 mm body, quad flat no-lead / micro lead frame package (mlf) 20m2 20-pad, 3 x 3 x 0.85 mm body, very thin quad flat no lead package (vqfn)
13 8246bs?avr?09/11 attiny2313a/4313 notes: 1. for speed vs. supply voltage, see section 22.3 ?speed? on page 199 . 2. all packages are pb-free, halide-free and fully green, and th ey comply with the european directive for restriction of hazard- ous substances (rohs). 3. code indicators: ? h: nipdau lead finish ? u or n: matte tin ? r: tape & reel 4. can also be supplied in wafer form. contact your local atme l sales office for ordering information and minimum quantities. 5. nipdau finish 6. topside markings: ? 1st line: t4313 ? 2nd line: axx ? 3rd line: xxx 6.2 attiny4313 speed (mhz) (1) supply voltage (v) temperature range package (2) ordering code (3) 20 1.8 ? 5.5 industrial (-40 c to +85 c) (4) 20p3 attiny4313-pu 20s attiny4313-su attiny4313-sur 20m1 attiny4313-mu attiny4313-mur 20m2 (5)(6) attiny4313-mmh attiny4313-mmhr package type 20p3 20-lead, 0.300" wide, plastic dual inline package (pdip) 20s 20-lead, 0.300" wide, plastic gull wing small outline package (soic) 20m1 20-pad, 4 x 4 x 0.8 mm body, quad flat no-lead/micro lead frame package (mlf) 20m2 20-pad, 3 x 3 x 0.85 mm body, very thin quad flat no lead package (vqfn)
14 8246bs?avr?09/11 attiny2313a/4313 7. packaging information 7.1 20p3 2 3 25 orch a rd p a rkw a y sa n jo s e, ca 951 3 1 title drawing no. r rev. 20p 3 , 20-le a d (0. 3 00"/7.62 mm wide) pl as tic d ua l inline p a ck a ge (pdip) d 20p 3 2010-10-19 pin 1 e1 a1 b e b1 c l s eating plane a d e eb ec common dimen s ion s (unit of me asu re = mm) s ymbol min nom max note a ? ? 5. 33 4 a1 0. 38 1 ? ? d 25.49 3 ? 25.9 8 4 note 2 e 7.620 ? 8 .255 e1 6.096 ? 7.112 note 2 b 0. 3 56 ? 0.559 b1 1.270 ? 1.551 l 2.921 ? 3 . 8 10 c 0.20 3 ? 0. 3 56 eb ? ? 10.922 ec 0.000 ? 1.524 e 2.540 typ note s : 1. thi s p a ck a ge conform s to jedec reference m s -001, v a ri a tion ad. 2. dimen s ion s d a nd e1 do not incl u de mold fl as h or protr us ion. mold fl as h or protr us ion s h a ll not exceed 0.25 mm (0.010").
15 8246bs?avr?09/11 attiny2313a/4313 7.2 20s
16 8246bs?avr?09/11 attiny2313a/4313 7.3 20m1 2325 orchard parkway san jose, ca 9 5131 title drawing no. r rev. 20m1 , 20-pad, 4 x 4 x 0.8 mm body, lead pitch 0.50 mm, a 20m1 10/27/04 2.6 mm exposed pad, micro lead frame package (mlf) a 0.70 0.75 0.80 a1 ? 0.01 0.05 a2 0.20 ref b 0.18 0.23 0.30 d 4.00 bsc d2 2.45 2.60 2.75 e 4.00 bsc e2 2.45 2.60 2.75 e 0.50 bsc l 0.35 0.40 0.55 side view pin 1 id pin #1 notch (0.20 r) bottom view top view note: reference jedec standard mo-220, fig . 1 (saw singulation) wggd-5. common dimensions (unit of measure = mm) symbol min nom max note d e e a2 a1 a d2 e2 0.08 c l 1 2 3 b 1 2 3
17 8246bs?avr?09/11 attiny2313a/4313 7.4 20m2 title drawing no. gpc rev. packa g e drawin g contact: p a ck a gedr a wing s @ a tmel.com 20m2 zfc b 20m2, 20-pad, 3 x 3 x 0.85 mm body, lead pitch 0.45 mm, 1.55 x 1.55 mm exposed pad, thermally enhanced plastic very thin quad flat no lead package (vqfn) 10/24/0 8 15 14 1 3 12 11 1 2 3 4 5 16 17 1 8 19 20 10 9 8 7 6 d2 e2 e b k l pin #1 ch a mfer (c 0. 3 ) d e s ide view a1 y pin 1 id bottom view top view a1 a c c0.1 8 ( 8 x) 0. 3 ref (4x) common dimen s ion s (unit of me asu re = mm) s ymbol min nom max note a 0.75 0. 8 0 0. 8 5 a1 0.00 0.02 0.05 b 0.17 0.22 0.27 c 0.152 d 2.90 3 .00 3 .10 d2 1.40 1.55 1.70 e 2.90 3 .00 3 .10 e2 1.40 1.55 1.70 e ? 0.45 ? l 0. 3 5 0.40 0.45 k 0.20 ? ? y 0.00 ? 0.0 8
18 8246bs?avr?09/11 attiny2313a/4313 8. errata the revision letters in this section refer to the revision of the corresponding attiny2313a/4313 device. 8.1 attiny2313a 8.1.1 rev. d no known errata. 8.1.2 rev. a ? c these device revisions were referred to as attiny2313/attiny2313v. 8.2 attiny4313 8.2.1 rev. a no known errata.
19 8246bs?avr?09/11 attiny2313a/4313 9. datasheet revision history 9.1 rev. 8246b ? 10/11 1. updated device status from preliminary to final. 2. updated document template. 3. added order codes for tape&reel devices, on page 259 and page 260 4. updated figures: ? figure 23-33 on page 223 ? figure 23-44 on page 228 ? figure 23-81 on page 247 ? figure 23-92 on page 252 5. updated sections: ? section 5. ?memories? on page 15 ? section 19. ?self-programming? on page 172 ? section 20. ?lock bits, fuse bits and device signature? on page 177 ? section 21. ?external programming? on page 183 ? section 26. ?ordering information? on page 259 9.2 rev. 8246a ? 11/09 1. initial revision. created from document 2543_t2313. 2. updated datasheet template. 3. added vqfn in the pinout figure 1-1 on page 2 . 4. added section 7.2 ?software bod disable? on page 34 . 5. added section 7.3 ?power reduction register? on page 34 . 6. updated table 7-2, ?sleep mode select,? on page 36 . 7. added section 7.5.3 ?bodcr ? brown-out detector control register? on page 37 . 8. added reset disable function in figure 8-1 on page 38 . 9. added pin change interrupts pcint1 and pcint2 in table 9-1 on page 47 . 10. added pcint17..8 and pcmsk2..1 in section 9.2 ?external interrupts? on page 48 . 11. added section 9.3.4 ?pcmsk2 ? pin change mask register 2? on page 52 . 12. added section 9.3.5 ?pcmsk1 ? pin change mask register 1? on page 52 . 13. updated section 10.2.1 ?alternate functions of port a? on page 61 . 14. updated section 10.2.2 ?alternate functions of port b? on page 62 . 15. updated section 10.2.3 ?alternate functions of port d? on page 66 . 16. added umsel1 and umsel0 in section 14.10.4 ?ucsrc ? usart control and sta- tus register c? on page 139 . 17. added section 15. ?usart in spi mode? on page 145 . 18. added usi buffer register (usibr) in section 16.2 ?overview? on page 155 and in fig- ure 16-1 on page 155 . 19. added section 16.5.4 ?usibr ? usi buffer register? on page 166 . 20. updated section 19.6.3 ?reading device signature imprint table from firmware? on page 175 .
20 8246bs?avr?09/11 attiny2313a/4313 21. updated section 19.7.1 ?spmcsr ? store program memory control and status regis- ter? on page 175 . 22. added section 20.3 ?device signature imprint table? on page 179 . 23. updated section 20.3.1 ?calibration byte? on page 180 . 24. changed bs to bs1 in section 20.6.13 ?reading the signature bytes? on page 189 . 25. updated section 22.2 ?dc characteristics? on page 198 . 26. added section 23.1 ?effect of power reduction? on page 206 . 27. updated characteristic plots in section 23. ?typical characteristics? for attiny2313a (pages 207 - 230), and added plots for attiny4313 (pages 231 - 254). 28. updated section 24. ?register summary? on page 255 . 29. updated section 26. ?ordering information? on page 259 , added the package type 20m2 and the ordering code -mmh (vqfn), and added the topside marking note.
21 8246bs?avr?09/11 attiny2313a/4313
8246bs?avr?09/11 headquarters international atmel corporation 2325 orchard parkway san jose, ca 95131 usa tel: 1(408) 441-0311 fax: 1(408) 487-2600 atmel asia limited unit 01-5 & 16, 19/f bea tower, millennium city 5 418 kwun tong road kwun tong, kowloon hong kong tel: (852) 2245-6100 fax: (852) 2722-1369 atmel munich gmbh business campus parkring 4 d-85748 garching b. munich germany tel: (+49) 89-31970-0 fax: (+49) 89-3194621 atmel japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (81) 3-3523-3551 fax: (81) 3-3523-7581 product contact web site www.atmel.com technical support avr@atmel.com sales contact www.atmel.com/contacts literature requests www.atmel.com/literature disclaimer: the information in this document is provided in connection with atmel products. no license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. except as set forth in atmel?s terms and condi- tions of sale located on atmel?s web site, atmel assumes no li ability whatsoever and disclaims any express, implied or statutor y warranty relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particu lar purpose, or non-infringement. in no event shall atmel be liable for any direct, indirect, consequential, punitive, special or i nciden- tal damages (including, without limitation, damages for loss of profits, business interruption, or loss of information) arising out of the use or inability to use this document, even if atme l has been advised of the possibility of such damages. atmel makes no representations or warranties with respect to the accuracy or comp leteness of the contents of this document and reserves the rig ht to make changes to specifications and product descriptions at any time without notice. atmel does not make any commitment to update the information contained her ein. unless specifically provided otherwise, atmel products are not suitable for, and shall not be used in, automotive applications. atmel?s products are not int ended, authorized, or warranted for use as components in applications in tended to support or sustain life. ? 2011 atmel corporation. all rights reserved. atmel ? , logo and combinations thereof, avr ? and others are registered trademarks or trade- marks of atmel corporation or its subsidiaries. other terms and product names may be trademarks of others.

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